View TS4621BEIJT_8972749.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

september 2011 doc id 022194 rev 2 1/48 48 ts4621b high-performance class-g stereo headphone amplifier with i 2 c volume control features power supply range: 2.3 v to 4.8 v 0.6 ma/channel quiescent current 2.1 ma current consumption with 100 w/channel (10 db crest factor) 0.006% typical thd+n at 1 khz 100 db typical psrr at 217 hz 100 db of snr a-weighted at g = 0 db zero pop and click i 2 c interface for volume control digital volume control range from -60 db to +4 db independent right and left channel shutdown control integrated high-efficiency step-down converter low software standby current: 5 a max output-coupling capacitors removed thermal shutdown flip-chip package: 1.65 mm x 1.65 mm, 400 m pitch, 16 bumps applications cellular phones, smart phones mobile internet devices pmp/mp3 players description the ts4621b is a class-g stereo headphone driver dedicated to high audio performance, high power efficiency and space-constrained applications. it is based on the core technology of a low power dissipation amplifier combined with a high- efficiency step-down dc/dc converter for supplying this amplifier. when powered by a battery, the internal step- down dc/dc converter generates the appropriate voltage to the amplifier depending on the amplitude of the audio signal to supply the headsets. it achieves a total 2.1 ma current consumption at 100 w output power (10 db crest factor). thd+n is 0.02 % maximum at 1 khz and psrr is 100 db at 217 hz, which ensures a high audio quality of the device in a wide range of environments. the traditionally bulky output coupling capacitors can be removed. a dedicated common-mode sense pin removes parasitic ground noise. the ts4621b is designed to be used with an output serial resistor. it ensures unconditional stability over a wide range of capacitive loads. the ts4621b is packaged in a tiny 16-bump flip-chip package with a pitch of 400 m. TS4621BEIJT - flip-chip balls are underneath pinout (top view) avdd sw inl- c1 cms sda agnd c2 hpvdd voutl voutr inl+ inr+ pvss scl inr- 4321 a b c d avdd sw inl- c1 cms sda agnd c2 hpvdd voutl voutr inl+ inr+ pvss scl inr- 4321 a b c d www.st.com
contents ts4621b 2/48 doc id 022194 rev 2 contents 1 absolute maximum ratings and operating conditions . . . . . . . . . . . . . 6 2 typical application sc hematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 i 2 c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1 i2c bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.2 control register cr1 - address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1.3 control register cr2 - address 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.4 control register cr3 - address 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.5 summary of output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 wake-up and standby time definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3 overview of the class-g, 2-level headphone amplifier . . . . . . . . . . . . . . . 31 4.4 external component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.1 step-down inductor selection (l1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.2 step-down output capacitor selection (ct) . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.3 full capacitive inverter capacitors selection (c12 and css) . . . . . . . . . 34 4.4.4 power supply decoupling capacitor selection (cs) . . . . . . . . . . . . . . . . . 34 4.4.5 input coupling capacitor selection (cin) . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.4.6 low-pass output filter (rout and cout) and iec 61000-4-2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4.7 integrated input low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5 single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5.1 layout recommendations for single-ended operation . . . . . . . . . . . . . . 38 4.6 startup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.6.1 auto zero technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.6.2 input impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.7 layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.7.1 common mode sense layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.8 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
ts4621b contents doc id 022194 rev 2 3/48 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
list of figures ts4621b 4/48 doc id 022194 rev 2 list of figures figure 1. typical application schematics for the ts4621b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. scl and sda timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. start and stop condition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 figure 4. current consumption vs. power supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. standby current consumption vs. power supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. maximum output power vs. loadin-phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. maximum output power vs. loadout-of-phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. maximum output power vs. power supply voltage, rl = 16 . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. maximum output power vs. power supply voltage, rl = 32 . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. maximum output power vs. power supply voltage, rl = 47 . . . . . . . . . . . . . . . . . . . . . . 14 figure 11. maximum output voltage vs. power supply voltage, in-phase. . . . . . . . . . . . . . . . . . . . . . . 14 figure 12. maximum output voltage vs. power supply voltage, out-of-phase . . . . . . . . . . . . . . . . . . . 14 figure 13. current consumption vs. total output power, rl = 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 14. current consumption vs. total output power, rl = 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 15. current consumption vs. total output power, rl = 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 16. current consumption vs. total output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 17. power dissipation vs. total output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 18. output impedance vs. frequency in hiz mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 19. differential input impedance vs. gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 20. thd+n vs. output power rl = 16 , in-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . . . . 15 figure 21. thd+n vs. output power rl = 16 , out-of-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . 15 figure 22. thd+n vs. output power rl = 16 , in-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . 16 figure 23. thd+n vs. output power rl = 16 , out-of-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . 16 figure 24. thd+n vs. output power rl = 16 , in-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . . . . 16 figure 25. thd+n vs. output power rl = 16 , out-of-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . 16 figure 26. thd+n vs. output power rl = 32 , in-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . . . . 16 figure 27. thd+n vs. output power rl = 32 , out-of-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . 16 figure 28. thd+n vs. output power rl = 32 , in-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . 17 figure 29. thd+n vs. output power rl = 32 , out-of-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . 17 figure 30. thd+n vs. output power rl = 32 , in-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . . . . 17 figure 31. thd+n vs. output power rl = 32 , out-of-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . 17 figure 32. thd+n vs. output power rl = 47 , in-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . . . . 17 figure 33. thd+n vs. output power rl = 47 , out-of-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . 17 figure 34. thd+n vs. output power rl = 47 , in-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . 18 figure 35. thd+n vs. output power rl = 47 , out-of-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . 18 figure 36. thd+n vs. output power rl = 47 , in-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . . . . 18 figure 37. thd+n vs. output power rl = 47 , out-of-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . 18 figure 38. thd+n vs. frequency rl = 16 , in-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 39. thd+n vs. frequency rl = 16 , out-of-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . . . . 18 figure 40. thd+n vs. frequency rl = 16 , in-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 41. thd+n vs. frequency rl = 16 , out-of-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . 19 figure 42. thd+n vs. frequency rl = 16 , in-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 43. thd+n vs. frequency rl = 16 , out-of-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . . . . 19 figure 44. thd+n vs. frequency rl = 32 , in-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 45. thd+n vs. frequency rl = 32 , out-of-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . . . . 19 figure 46. thd+n vs. frequencyrl = 32 , in-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 47. thd+n vs. frequency rl = 32 , out-of-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . 20 figure 48. thd+n vs. frequency rl = 32 , in-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ts4621b list of figures doc id 022194 rev 2 5/48 figure 49. thd+n vs. frequency rl = 32 , out-of-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . . . . 20 figure 50. thd+n vs. frequency rl = 47 , in-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 51. thd+n vs. frequency rl = 47 , out-of-phase, v cc = 2.5 v . . . . . . . . . . . . . . . . . . . . . . . 20 figure 52. thd+n vs. frequency rl = 47 , in-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 53. thd+n vs. frequency rl = 47 , out-of-phase, v cc = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . 21 figure 54. thd+n vs. frequency rl = 47 , in-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 55. thd+n vs. frequency rl = 47 , out-of-phase, v cc = 4.8 v . . . . . . . . . . . . . . . . . . . . . . . 21 figure 56. thd+n vs. frequency rl = 10 k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 57. thd+n vs. frequency rl = 600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 58. thd+n vs. output voltage rl = 10 k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 59. thd+n vs. output voltage rl = 600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 60. thd+n vs. input voltage, hiz left and right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 figure 61. cmrr vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 62. psrr vs. frequencyv cc = 2.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 63. psrr vs. frequencyv cc = 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 64. psrr vs. frequencyv cc = 4.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 65. output signal spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 66. crosstalk vs. frequencyrl = 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 67. crosstalk vs. frequencyrl = 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 68. crosstalk vs. frequencyrl = 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 69. crosstalk vs. frequencyrl = 10 k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 70. wake-up time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 71. shutdown time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 72. i2c write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 73. i2c read operations1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 74. flowchart for short-circuit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 75. ts4621b architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 76. efficiency comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 77. class-g operating with a music sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 78. typical application schematic with iec 61000-4-2 esd protection . . . . . . . . . . . . . . . . . . 36 figure 79. single-ended input configuration1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 80. single-ended input configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 81. incorrect ground connection for single-ended option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 82. correct ground connection for single-ended option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 83. common mode sense layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 84. demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 85. copper layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 86. copper layer and overlay layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 87. ts4621b footprint recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 figure 88. pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 89. marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 90. flip-chip - 16 bumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 91. device orientation in tape pocket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
absolute maximum ratings and operating conditions ts4621b 6/48 doc id 022194 rev 2 1 absolute maximum ratings and operating conditions table 1. absolute maximum ratings symbol parameter value unit v cc supply voltage (1) during 1ms. 1. all voltage values are measur ed with respect to the ground pin. 5.5 v v in+ ,v in- input voltage referred to ground +/- 1.2 v t stg storage temperature -65 to +150 c t j maximum junction temperature (2) 2. thermal shutdown is activated when ma ximum junction temperature is reached. 150 c r thja thermal resistance junction to ambient (3) 3. the device is protected from ov er-temperature by a thermal shut down mechanism, active at 150 c. 200 c/w p d power dissipation internally limited (4) 4. exceeding the power derating curves for long periods may prov oke abnormal operation. esd human body model (hbm) (5) all pins voutr, voutl vs. agnd 5. human body model: a 100 pf capacit or is charged to the specified voltage, then discharged through a 1.5 k resistor between two pins of the device. this is done for all couples of conn ected pin combinations while the other pins are floating. 2 4 kv machine model (mm), min. value (6) 6. machine model: a 200 pf capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (int ernal resistor < 5 ). this is done for all couples of connected pin combinations whil e the other pins are floating. 100 v charge device model (cdm) all pins voutr, voutl 500 750 v iec61000-4-2 level 4, contact (7) iec61000-4-2 level 4, air discharge (7) 7. the measurement is performed on an evaluati on board, with esd protection emif02-av01f3. +/- 8 +/- 15 kv lead temperature (soldering, 10 sec) 260 c
ts4621b absolute maximum rati ngs and operating conditions doc id 022194 rev 2 7/48 table 2. operating conditions symbol parameter value unit v cc supply voltage 2.3 to 4.8 v hpvdd internal step-down dc output voltages high rail voltage low rail voltage 1.9 1.2 v sda, scl input voltage range gnd to v cc v r l load resistor 16 c l load capacitor serial resistor of 12 minimum , r l 16 0.8 to 100 nf t oper operating free air temperature range -40 to +85 c r thja flip-chip thermal resistance junction to ambient 90 c/w
typical application schematics ts4621b 8/48 doc id 022194 rev 2 2 typical application schematics figure 1. typical application schematics for the ts4621b table 3. ts4621b pin description pin number pin name pin definition a1 sw switching node of the buck converter a2 avdd analog supply voltage, connect to battery a3 voutl output signal for left audio channel a4 inl- negative input signal for left audio channel b1 agnd device ground b2 c1 flying capacitor terminal for internal negative supply generator b3 hpvdd buck converter output, power supply for amplifier b4 inl+ positive input signal for left audio channel c1 c2 flying capacitor terminal for internal negative supply generator c2 pvss negative supply generator output c3 cms common mode sense, to be connected as close as possible to the ground of headphone/line out plug c4 inr+ positive input signal for right audio channel d1 sda i2c data signal, up to v cc tolerant input d2 scl i2c clock signal, up to v cc tolerant input d3 voutr output signal for right audio channel d4 inr- negative input signal for right audio channel ro u t 12 ohm s min. ro u t 12 ohm s min. co u t 0. 8 nf min. co u t 0. 8 nf min. cin 1 u f cin 1 u f cin 1 u f cin 1 u f 1 2 3 j1 c12 2.2 u f c s 2.2 u f c ss 2.2 u f ct 10 u f l1 3 . 3 u h v ba t i2c bus + - + - i2c neg a tive su pply po s itive su pply agnd c1 c2 s da s cl avdd inl- inl+ inr+ inr- vo u tl vo u tr cm s level detector level detector s w hpvdd pv ss neg a tive left inp u t po s itive left inp u t neg a tive right inp u t po s itive right inp u t am06119
ts4621b typical application schematics doc id 022194 rev 2 9/48 table 4. ts4621b component description (1) component value description cs 2.2 f decoupling capacitors for v cc . a 2.2 f capacitor is sufficient for proper decoupling of the ts4621b. an x5r dielectric and 10 v rating voltage is recommended to minimize c/ v when v cc =4.8v. must be placed as close as possible to the ts4621b to minimize parasitic inductance and resistance. c12 2.2 f capacitor for internal negative power supply operation. an x5r dielectric and 6.3 v rating voltage is recommended to minimize c/ v when hpvdd = 1.9 v. must be placed as close as possible to the ts4621b to minimize parasitic inductance and resistance. c ss 2.2 f filtering capacitor for internal negative power supply. an x5r dielectric and 6.3 v rating voltage is recommended to minimize c/ v when hpvdd = 1.9 v. c in input coupling capacitor that forms with rin rindiff/2 a first-order high- pass filter with a -3 db cutoff frequency fc. for example, at maximum gain g=4db, rin=12.5k , c in = 1 f, therefore fc = 13 hz. c out 0.8 to 100 nf output capacitor of 0.8 nf minimum to 100 nf maximum. this capacitor is mandatory for operation of the ts4621b. r out 12 min. output resistor in-series wit h the ts4621b output. this 12 minimum resistor is mandatory fo r operation of the ts4621b. l1 3.3 h inductor for internal dc/dc step-down converter. references of inductors: refer to section 4.4.1 for more information. c t 10 f tank capacitor for internal dc/dc step-down converter. an x5r dielectric and 6.3 v rating voltage is recommended to minimize c/ v when hpvdd = 1.9 v. refer to section 4.4.2 for more information. 1. refer to section 4.4 for a complete description of each component. cin 1 2 rin fc ------------------------------------------ =
electrical characteristics ts4621b 10/48 doc id 022194 rev 2 3 electrical characteristics table 5. electrical characteristics of the i2c interface for v cc = +3.6 v, agnd = 0 v, t amb = 25c (unless otherwise specified) symbol parameter min. typ. max. unit v il low level input voltage on sda, scl pins 0.6 v v ih high level input voltage on sda, scl pins 1.2 v v ol low level output voltage, sda pin, i sink = 3ma 0.4 v i in input current on sda, scl 10 a v sda scl , 600k -------------------------------- - table 6. electrical characteristics of the amplifier for v cc = +3.6 v, agnd = 0 v, r l = 32 + 15 , t amb = 25 c (unless otherwise specified) symbol parameter min. typ. max. unit i cc quiescent supply current, no input signal, both channels enabled 1.2 1.5 ma i s supply current, with input modulation, both channels enabled, hpvdd = 1.2 v, output power per channel, f=1khz pout = 100 w at 3 db crest factor pout = 500 w at 3 db crest factor pout = 1mw at 3db crest factor pout = 100 w at 10 db crest factor pout = 500 w at 10 db crest factor pout = 1 mw at 10 db crest factor 2.3 3.7 4.7 2.1 3.1 3.9 3.5 5 6.5 ma i stby standby current, no input signal, i2c cr1 = 01h v sda = 0 v, v scl = 0 v 0.6 5 a v in input differential voltage range (1) 1v rms v oo output offset voltage no input signal -500 +500 v v out maximum output voltage, in-phase signals r l = 16 , thd+n = 1% max, f = 1 khz r l = 47 , thd+n = 1% max, f = 1 khz r l = 10 k , r s = 15 , c l = 1 nf, thd+n = 1% max, f = 1 khz 0.6 1.0 1.0 0.8 1.1 1.3 v rms thd+n total harmonic distortion + noise, g = 0 db v out = 700 mvrms, f = 1 khz v out = 700 mvrms, 20 hz < f < 20 khz 0.006 0.05 0.02 % psrr power supply rejection ratio (1) , v ripple = 200 mv pp , grounded inputs f = 217 hz, g = 0 db, r l 16 f = 10 khz, g = 0 db, r l 16 90 100 70 db
ts4621b electrical characteristics doc id 022194 rev 2 11/48 cmrr common mode rejection ratio f = 1 khz , g = 0 db, v ic = 200 mv pp f = 20 hz to 20 khz , g = 0 db, v ic = 200 mv pp 65 45 db crosstalk channel separation r l = 32 + 15 , g = 0 db, f = 1 khz, p o = 10 mw r l = 10 k , g = 0 db, f = 1 khz, v out =1 vrms 60 80 100 110 db snr signal-to-noise ratio, a-weighted, v out = 1 v rms , thd+n < 1%, f = 1 khz (1) g = +4 db g = +0 db 99 100 db onoise output noise voltage, a-weighted (1) g = +4 db g = +0 db 911 9 vrms g gain range with gain (db) = 20 x log[(v out l/r)/(inl/r+ - inl/r-)] -60 +4 db mute inl/r+ - inl/r- = 1 v rms -80 db - gain step size error -0.5 +0.5 step- size - gain error (g = +4 db) -0.45 +0.42 db r indiff differential input impedance 25 34 k input impedance during wake-up phase (referred to ground) 2 k z out output impedance when cr1 = 00h (negative supply is on and amplifier output stages are off) (1) f < 40 khz f = 6 mhz f = 36 mhz 10 500 75 k t wu wake-up time (2) 12 16 ms t stby standby time 100 s t atk attack time. setup time between low rail and high rail voltages of internal step-down dc/dc converter 100 s t dcy decay time 50 ms 1. guaranteed by design and parameter correlation. 2. refer to the application information in section 4.2 on page 30 . table 6. electrical characteristics of the amplifier for v cc = +3.6 v, agnd = 0 v, r l = 32 + 15 , t amb = 25 c (unless otherwise specified) (continued) symbol parameter min. typ. max. unit
electrical characteristics ts4621b 12/48 doc id 022194 rev 2 figure 2. scl and sda timing diagram figure 3. start and stop condition timing diagram table 7. timing characteristics of the i2c interface for i2c interface signals over recommended operating conditions (unless otherwise specified) symbol parameter min. typ. max. unit f scl frequency, scl 400 khz t d(h) pulse duration, scl high 0.6 s t d(l) pulse duration, scl low 1.3 s t st1 setup time, sda to scl 100 ns t h1 hold time, scl to sda 0 ns t f bus free time between stop and start condition 1.3 s t st2 setup time, scl to start condition 0.6 s t h2 hold time, start condition to scl 0.6 s t st3 setup time, scl to stop condition 0.6 s s cl s da t d(h) t d(l) t s t1 t h1 am0611 3 am06114 t s t 3 s cl s da t s t2 s t a rt condition s top condition t h2 t f
ts4621b electrical characteristics doc id 022194 rev 2 13/48 figure 4. current consumption vs. power supply voltage figure 5. standby current consumption vs. power supply voltage 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 no load; no input signal both channels enabled ta = 25 c quiscent supply current i cc (ma) power supply voltage vcc (v) no load; no input signal sda=scl = 0v ta = 25 c figure 6. maximum output power vs. load in-phase figure 7. maximum output power vs. load out-of-phase 10 100 1k 0 10 20 30 40 50 60 70 80 vcc=2.3v vcc=3.6v inputs = 0 , f = 1khz thd+n = 1% tamb = 25 c vcc=4.8v output power (mw) rl load resistance ( ) 10 100 1k 0 10 20 30 40 50 60 70 80 vcc=2.3v vcc=3.6v inputs = 180 , f = 1khz thd+n = 1% tamb = 25 c vcc=4.8v output power (mw) rl load resistance ( ) figure 8. maximum output power vs. power supply voltage, rl = 16 figure 9. maximum output power vs. power supply voltage, rl = 32 2.3 2.7 3.1 3.5 3.9 4.3 4.7 0 20 40 60 80 100 120 thd+n=10% (180 ) thd+n=10% (0 ) thd+n=1% (0 ) rl = 16 , f = 1khz bw < 30khz, tamb = 25 c thd+n=1% (180 ) output power (mw) power supply voltage vcc (v) 2.3 2.7 3.1 3.5 3.9 4.3 4.7 0 20 40 60 80 thd+n=10% (180 ) thd+n=10% (0 ) thd+n=1% (0 ) rl = 32 , f = 1khz bw < 30khz, tamb = 25 c thd+n=1% (180 ) output power (mw) power supply voltage vcc (v)
electrical characteristics ts4621b 14/48 doc id 022194 rev 2 figure 10. maximum output power vs. power supply voltage, rl = 47 figure 11. maximum output voltage vs. power supply voltage, in-phase 2.3 2.7 3.1 3.5 3.9 4.3 4.7 0 20 40 60 thd+n=10% (180 ) thd+n=10% (0 ) thd+n=1% (0 ) rl = 47 , f = 1khz bw < 30khz, tamb = 25 c thd+n=1% (180 ) output power (mw) power supply voltage vcc (v) 2.3 2.7 3.1 3.5 3.9 4.3 4.7 700 800 900 1000 1100 1200 1300 1400 1500 1600 10 k 600 60 47 16 f = 1khz bw < 30khz, tamb = 25 c inputs = 0 , thd+n = 1% 32 output voltage (mvrms) power supply voltage vcc (v) figure 12. maximum output voltage vs. power supply voltage, out-of-phase figure 13. current consumption vs. total output power, rl = 16 2.3 2.7 3.1 3.5 3.9 4.3 4.7 700 800 900 1000 1100 1200 1300 1400 1500 1600 10 k 600 60 47 16 f = 1khz bw < 30khz, tamb = 25 c inputs = 180 , thd+n=1% 32 output voltage (mvrms) power supply voltage vcc (v) 0.1 1 10 1 10 100 vcc=4.8v vcc=3.6v vcc=2.3v both channels enabled rl = 16 , f = 1khz ta = 25 c crest factor = 3db supply current i s (ma) total output power (mw) figure 14. current consumption vs. total output power, rl = 32 figure 15. current consumption vs. total output power, rl = 47 0.1 1 10 1 10 100 vcc=4.8v vcc=3.6v vcc=2.3v both channels enabled rl = 32 , f = 1khz ta = 25 c crest factor = 3db supply current i s (ma) total output power (mw) 0.1 1 10 1 10 100 vcc=4.8v vcc=3.6v vcc=2.3v both channels enabled rl = 47 , f = 1 khz ta = 25 c crest factor = 3db supply current i s (ma) total output power (mw)
ts4621b electrical characteristics doc id 022194 rev 2 15/48 figure 16. current consumption vs. total output power figure 17. power dissipation vs. total output power 0.1 1 1 10 100 crest factor=3db crest factor=10db both channels enabled rl = 47 , f = 1khz ta = 25 c, vcc = 3.6v supply current i s (ma) total output power (mw) 0.1 1 10 1 10 100 r = 47 r = 32 r = 16 both channels enabled f = 1khz, ta = 25 c crest factor = 3db power dissipation (mw) total output power (mw) figure 18. output impedance vs. frequency in hiz mode figure 19. differential input impedance vs. gain input floating input grounded vcc=2.3v to 4.8v hiz; right & left osc level=0.5v rms ta = 25 c -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 30 40 50 60 70 80 vcc=2.3v to 4.8v ta = 25 c differential input impedance (k ) gain (db) figure 20. thd+n vs. output power rl = 16 , in-phase, v cc = 2.5 v figure 21. thd+n vs. output power rl = 16 , out-of-phase, v cc = 2.5 v f=80hz f=1khz f=8khz vcc = 2.5v, rl = 16 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 2.5v, rl = 16 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c
electrical characteristics ts4621b 16/48 doc id 022194 rev 2 figure 22. thd+n vs. output power rl = 16 , in-phase, v cc = 3.6 v figure 23. thd+n vs. output power rl = 16 , out-of-phase, v cc = 3.6 v f=80hz f=1khz f=8khz vcc = 3.6v, rl = 16 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 3.6v, rl = 16 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 24. thd+n vs. output power rl = 16 , in-phase, v cc = 4.8 v figure 25. thd+n vs. output power rl = 16 , out-of-phase, v cc = 4.8 v f=80hz, 1khz f=8khz vcc = 4.8v, rl = 16 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz, 1khz f=8khz vcc = 4.8v, rl = 16 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 26. thd+n vs. output power rl = 32 , in-phase, v cc = 2.5 v figure 27. thd+n vs. output power rl = 32 , out-of-phase, v cc = 2.5 v f=80hz f=1khz f=8khz vcc = 2.5v, rl = 32 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 2.5v, rl = 32 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c
ts4621b electrical characteristics doc id 022194 rev 2 17/48 figure 28. thd+n vs. output power rl = 32 , in-phase, v cc = 3.6 v figure 29. thd+n vs. output power rl = 32 , out-of-phase, v cc = 3.6 v f=80hz f=1khz f=8khz vcc = 3.6v, rl = 32 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 3.6v, rl = 32 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 30. thd+n vs. output power rl = 32 , in-phase, v cc = 4.8 v figure 31. thd+n vs. output power rl = 32 , out-of-phase, v cc = 4.8 v f=80hz f=1khz f=8khz vcc = 4.8v, rl = 32 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 4.8v, rl = 32 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 32. thd+n vs. output power rl = 47 , in-phase, v cc = 2.5 v figure 33. thd+n vs. output power rl = 47 , out-of-phase, v cc = 2.5 v f=80hz f=1khz f=8khz vcc = 2.5v, rl = 47 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 2.5v, rl = 47 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c
electrical characteristics ts4621b 18/48 doc id 022194 rev 2 figure 34. thd+n vs. output power rl = 47 , in-phase, v cc = 3.6 v figure 35. thd+n vs. output power rl = 47 , out-of-phase, v cc = 3.6 v f=80hz f=1khz f=8khz vcc = 3.6v, rl = 47 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 3.6v, rl = 47 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 36. thd+n vs. output power rl = 47 , in-phase, v cc = 4.8 v figure 37. thd+n vs. output power rl = 47 , out-of-phase, v cc = 4.8 v f=80hz f=1khz f=8khz vcc = 4.8v, rl = 47 g = 4db, inputs = 0 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz vcc = 4.8v, rl = 47 g = 4db, inputs = 180 bw < 30khz, tamb = 25 c figure 38. thd+n vs. frequency rl = 16 , in-phase, v cc = 2.5 v figure 39. thd+n vs. frequency rl = 16 , out-of-phase, v cc = 2.5 v po=1mw po=15mw rl = 16 vcc = 2.5v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=15mw rl = 16 vcc = 2.5v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20
ts4621b electrical characteristics doc id 022194 rev 2 19/48 figure 40. thd+n vs. frequency rl = 16 , in-phase, v cc = 3.6 v figure 41. thd+n vs. frequency rl = 16 , out-of-phase, v cc = 3.6 v po=1mw po=15mw rl = 16 vcc = 3.6v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=15mw rl = 16 vcc = 3.6v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 42. thd+n vs. frequency rl = 16 , in-phase, v cc = 4.8 v figure 43. thd+n vs. frequency rl = 16 , out-of-phase, v cc = 4.8 v po=1mw po=15mw rl = 16 vcc = 4.8v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=15mw rl = 16 vcc = 4.8v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 44. thd+n vs. frequency rl = 32 , in-phase, v cc = 2.5 v figure 45. thd+n vs. frequency rl = 32 , out-of-phase, v cc = 2.5 v po=1mw po=10mw rl = 32 vcc = 2.5v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 32 vcc = 2.5v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20
electrical characteristics ts4621b 20/48 doc id 022194 rev 2 figure 46. thd+n vs. frequency rl = 32 , in-phase, v cc = 3.6 v figure 47. thd+n vs. frequency rl = 32 , out-of-phase, v cc = 3.6 v po=1mw po=10mw rl = 32 vcc = 3.6v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 32 vcc = 3.6v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 48. thd+n vs. frequency rl = 32 , in-phase, v cc = 4.8 v figure 49. thd+n vs. frequency rl = 32 , out-of-phase, v cc = 4.8 v po=1mw po=10mw rl = 32 vcc = 4.8v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 32 vcc = 4.8v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 50. thd+n vs. frequency rl = 47 , in-phase, v cc = 2.5 v figure 51. thd+n vs. frequency rl = 47 , out-of-phase, v cc = 2.5 v po=1mw po=10mw rl = 47 vcc = 2.5v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 47 vcc = 2.5v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20
ts4621b electrical characteristics doc id 022194 rev 2 21/48 figure 52. thd+n vs. frequency rl = 47 , in-phase, v cc = 3.6 v figure 53. thd+n vs. frequency rl = 47 , out-of-phase, v cc = 3.6 v po=1mw po=10mw rl = 47 vcc = 3.6v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 47 vcc = 3.6v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 54. thd+n vs. frequency rl = 47 , in-phase, v cc = 4.8 v figure 55. thd+n vs. frequency rl = 47 , out-of-phase, v cc = 4.8 v po=1mw po=10mw rl = 47 vcc = 4.8v g = 0db inputs = 0 bw < 20khz tamb = 25 c 20k 20 po=1mw po=10mw rl = 47 vcc = 4.8v g = 0db inputs = 180 bw < 20khz tamb = 25 c 20k 20 figure 56. thd+n vs. frequency rl = 10 k figure 57. thd+n vs. frequency rl = 600 vo=1vrms vo=100mvrms rl = rc network + 10k vcc = 2.3v to 4.8v g = 0db, inputs = 0 & 180 bw < 20khz, tamb = 25 c 20k 20 vo=1vrms vo=100mvrms rl = rc network + 600 vcc = 2.3v to 4.8v g = 0db, inputs = 0 & 180 bw < 20khz, tamb = 25 c 20k 20
electrical characteristics ts4621b 22/48 doc id 022194 rev 2 figure 58. thd+n vs. output voltage rl = 10 k figure 59. thd+n vs. output voltage rl = 600 f=80hz f=1khz f=8khz rl = rc network + 10k vcc = 2.3v to 4.8v, g = 4db inputs = 0 & 180 bw < 30khz, tamb = 25 c f=80hz f=1khz f=8khz rl = rc network + 600 vcc = 2.3v to 4.8v, g = 4db inputs = 0 & 180 bw < 30khz, tamb = 25 c figure 60. thd+n vs. input voltage, hiz left and right figure 61. cmrr vs. frequency line in f=8khz line in f=1khz reference f=80hz, 1khz, 8khz line in f=80hz hiz left & right vcc = 2.3v to 4.8v zout generator = 1k bw < 30khz, tamb = 25 c 100 1000 10000 -80 -70 -60 -50 -40 -30 -20 -10 0 20k 20 figure 62. psrr vs. frequency v cc = 2.5 v figure 63. psrr vs. frequency v cc = 3.6 v 100 1000 10000 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=-6db g=0db g=4db 20k 20 100 1000 10000 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=-6db g=0db g=4db 20k 20
ts4621b electrical characteristics doc id 022194 rev 2 23/48 figure 64. psrr vs. frequency v cc = 4.8 v figure 65. output signal spectrum 100 1000 10000 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=-6db g=0db g=4db 20k 20 figure 66. crosstalk vs. frequency rl = 16 figure 67. crosstalk vs. frequency rl = 32 100 1000 10000 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 20k 20 100 1000 10000 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 20k 20 figure 68. crosstalk vs. frequency rl = 47 figure 69. crosstalk vs. frequency rl = 10 k 100 1000 10000 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 20k 20 100 1000 10000 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 20k 20
electrical characteristics ts4621b 24/48 doc id 022194 rev 2 figure 70. wake-up time figure 71. shutdown time vout 2ms/div 20mv/div sda 2 ms/div 1v/div vout 10s/div 100mv/div i2c ack after shutdown command
ts4621b application information doc id 022194 rev 2 25/48 4 application information 4.1 i 2 c bus interface in compliance with the i2c protocol, the ts4621b uses a serial bus to control the chip?s functions with the clock (scl) and data (sda) wires. these two lines are bi-directional (open collector) and require an external pull-up resistor (typically 10 k ). the maximum clock frequency in fast mode specified by the i2c standard is 400 khz, which the ts4621b supports. in this application, the ts4621b is always the sl ave device and the controlling microcontroller mcu is the master device. the slave address of the ts4621b is 1100 000x (c0h). ta bl e 8 summarizes the pin descriptions for the i2c bus interface. 4.1.1 i2c bus operation the host mcu can write to the ts4621b control register to control the ts4621b, and read from the control register to obtain a configuration from the ts4621b. the ts4621b is addressed by the byte consisting of the 7-bit slave address and the r/w bit. there are four control registers ( ta bl e 1 0 ) named cr1 to cr4. in read mode, all the control registers can be accessed. in write mode, only cr1, cr2 and cr3 can be addressed. table 8. pin description of the i2c bus interface pin functional description sda serial data pin scl clock input pin table 9. first byte after the start message for addressing the device a6 a5 a4 a3 a2 a1 a0 r/w 1100000x table 10. summary of control registers description register address d7 d6 d5 d4 d3 d2 d1 d0 cr1 1 hp_en_l hp_en_r 0 0 sc_l sc_r t_sh sws cr2 volume control 2 mute_l mute_r volume control 0 cr3 3 0 0 0 0 0 0 hiz_l hiz_r cr4 identification 4 01000000
application information ts4621b 26/48 doc id 022194 rev 2 table 11. control registers at power-up writing to the control registers to write data to the ts4621b, after the "start" message the mcu must: send the i2c 7-bit slave address and a low level for the r/w bit. send the register address to write to. send the data bytes (control register settings). all bytes are sent msb first. the transfer of written data ends with a "stop" message. when transmitting several data bytes, the data can be written without having to repeat the "start" message or send the byte with the slave addre ss. if several bytes are transmitted, they will be written repeatedly to cr1, cr2 and cr3. figure 72. i2c write operations reading from the control registers to read data from the ts4621b, after the "start" message the mcu must: send the i2c 7-bit slave address and a low level for the r/w bit. send the register address to read. send the i2c 7-bit slave address and a high level for the r/w bit. receive the data (control register value). all bytes are read msb first. the transfer of read data ends with a "stop" message. when transmitting several data bytes, the data can be read without having to repeat the "start" message or send the byte with the slave address. if several bytes are transmitted, they are read repeatedly from cr1, cr2, cr3 and cr4. description register address d7 d6 d5 d4 d3 d2 d1 d0 cr1 1 0 0 0 0 0 0 0 1 cr2 2 1 1 0 0 0 0 0 0 cr3 3 0 0 0 0 0 0 0 0 cr4 4 0 1 0 0 0 0 0 0 s da s 1100 0 0 ack 00 a7 d7 a0 a1 ack p s t a rt condition s lave device addre ss data byte s r/w acknowledge from s l a ve acknowledge from s l a ve s top condition a6 d6 d1 d0 d7 d6 d1 d0 regi s ter addre ss cr x crx+1 ack ack am06115
ts4621b application information doc id 022194 rev 2 27/48 figure 73. i2c read operations1 4.1.2 control regist er cr1 - address 1 amplifier output short-circuit detection: bits sc_l and sc_r the amplifier?s outputs are protected from short- circuits that might accidentally occur during manipulation of the device. in a typical application, if a short-circuit arises on the jack plug, there will be no detection because of the serial resistor pr esent on the amplif ier output, thus the output curr ent threshold will not be reached. to be active, the detection has to occur directly on the amplifier?s output with a signal modulation on the inputs of the ts4621b. this detection is depicted in figure 74 . figure 74. flowchart for short-circuit detection am06116 s da s 110 000 ack 00 a7 a0 d7 p s t a rt condition device addre ss data byte s r/w acknowledge fom s l a ve not acknowledge s top condition d0 d7 d0 regi s ter addre ss crx crx+1 ack a a s repe a t s t a rt condition 110 001 00 ack ack device addre ss r/w am06117 co u nter = 0 t s 4621b power off co u nter = co u nter + 1 t s 4621b power on timeo u t = 40 m s t s 4621b power on w a it 40 m s s et fl a g s c_l or s c_r to 1 s et fl a g hiz_l or hiz_r to 1 s hortc u t detection s hortc u t detection s hortc u t detection & timeo u t = 0 s hortc u t detection re s et co u nter < 3 co u nter = 3
application information ts4621b 28/48 doc id 022194 rev 2 if a short-circuit is detected three consecutive ti mes on one channel, a flag is raised in the i2c read register cr1. sc_l: equals 0 during normal operation, equals 1 when a short-circuit is detected on the left channel. sc_r: equals 0 during normal operation, equa ls 1 when a short-circuit is detected on the right channel. the corresponding channel?s output stage is then set to high impedance mode. an i2c read command allows the reading of the sc_l and sc_r flags but does not reset them. an i2c write command has to be sent to cr1 to reset the flags to 0 and restore normal operation. thermal shutdown protection: bit t_sh a thermal shutdown protection is implemented to protect the device from overheating. if the temperature rises above the thermal junction of 150c, the device is put into standby mode and a flag is raised in the read register cr1. t_sh: equals 0 during normal operation, equals 1 when a thermal shutdown is detected. when the temperature decreases to safe levels, the circuit switches back to normal operation and the corresponding flag is cleared. software shutdown: bit sws when sws equals 1, the device is set to i2c software shutdown. when sws equals 0, the negative supply and buck converters are activated. channel activation: bits hp_en_l and hp_en_r when hp_en_l or hp_en_r equals 1, the corresponding amplifier channel is enabled.
ts4621b application information doc id 022194 rev 2 29/48 4.1.3 control regist er cr2 - address 2 mute function: bits mute_l and mute_r in the volume register, mute_l and mute_r are dedicated to enabling the mute function, independently of the channel. when mute_l and mute_r are set to 1, the mute function is enabled on the corresponding channel and t he gain is set to -80 db. when mute_l and mute_r are set to 0, the i2c gain level is applied to the channel. 4.1.4 control regist er cr3 - address 3 high output impedance mode: bits hiz_l and hiz_r the ts4621b features a high-output impedance mode used, for example, to share the headphone jack with the audio and composite video signal. to set this mode, you must set the hiz bit to 1 for the targeted output in the cr3 register. at this time, the considered output is in high-impedance mode with the following characteristics: maximum input voltage = -1.8 to +1.8 v output impedance = input impedance detected by the video driver. for an example, refer to chapter 3: electrical characteristics on page 10 or figure 18 . table 12. volume control register cr2 - address 2 volume control range: -60 db to +4 db d5 d4 d3 d2 d1 gain (in db) d5 d4 d3 d2 d1 gain (in db) 00000 -60 db 10000 -11 db 00001 -54 db 10001 -10 db 00010 -50.5 db 10010 -9 db 00011 -47 db 10011 -8 db 00100 -43 db 10100 -7 db 00101 -39 db 10101 -6 db 00110 -35 db 10110 -5 db 00111 -31 db 10111 -4 db 01000 -27 db 11000 -3 db 01001 -25 db 11001 -2 db 01010 -23 db 11010 -1 db 01011 -21 db 11011 0 db 01100 -19 db 11100 +1 db 01101 -17 db 11101 +2 db 01110 -15 db 11110 +3 db 01111 -13 db 11111 +4 db
application information ts4621b 30/48 doc id 022194 rev 2 4.1.5 summary of output impedance 4.2 wake-up and standby time definition the wake-up time of the ts4621b is guaranteed at 12 ms typical (refer to chapter 3: electrical characteristics ). however, since the ts4621b is activated with an i 2 c bus, the wake-up start procedure is as follows. 1. the master sends a start bit. 2. the master sends the device address. 3. the slave (ts4621b) answers by an acknowledge bit. 4. the master sends the register address. 5. the slave (ts4621b) answers by an acknowledge bit. 6. the master sends the output mode configuration (cr1). 7. if the ts4621b was previous ly in standby mode, the wake-up starts on the falling edge of the eighth clock signal (scl ) corresponding to the cr1 byte. 8. after 12 ms (de-pop sequence time), the ts4621b outputs are operational. the standby time is guaranteed as 100 s typical (refer to chapter 3 ). however, since the ts4621b is de-activated with an i 2 c bus, the standby time operates as follows. 1. the master sends a start bit. 2. the master sends the device address. 3. the slave (ts4621b) answers by an acknowledge bit. 4. the master sends the register address. 5. the slave (ts4621b) answers by an acknowledge bit. 6. the master sends the output mode configuration (cr1), which corresponds, in this case, to standby mode. 7. the standby time starts on the falling edge of the eighth clock signal (scl) corresponding to the cr1 byte. 8. after 100 s, the ts4621b is in standby mode. table 13. summary table for output impedance vs. output mode sws hiz hp_en output impedance maximum voltage allowed on output pin 1 0 0 20 to 40 less than 100 mv 1 0 1 20 to 40 less than 100 mv 1 1 0 about 10 k -0.3 v to avdd 1 1 1 about 10 k -0.3 v to avdd 0 0 0 20 to 40 less than 100 mv 0 0 1 less than 1 not applicable 0 1 0 see figure 18 -1.8 to +1.8 v 0 1 1 see figure 18 -1.8 to +1.8 v
ts4621b application information doc id 022194 rev 2 31/48 4.3 overview of the class-g, 2-level headphone amplifier the ts4621b uses what is referred to as class-g operating mode . this mode is a combination of the class-ab biasing technique and an adaptive power supply. for this device, the power supply uses two levels: 1.2 v and 1.9 v. to create the 1.2 v and 1.9 v levels, the device uses an internal high-efficiency step- down converter linked with a fully capacitive inve rter from avdd. thanks to these internally- generated symmetrical power supply voltages, the output of the amplifier can be biased at 0 v, thus eliminating the classical bulky dc blocking output capacitors (typically more than 100 f). figure 75. ts4621b architecture when an audio signal is playing with the ts4621 b, the class-g feature adjusts in real time the internal power supply voltage in order to achieve the best efficiency possible. in addition, thanks to the fast transient response of the internal dc/dc converters, the switching between 1.2 v and 1.9 v can be achieved without audio clipping. moreover, the out-of- audio band dc/dc switching frequency keeps the audio quality at a high level (distortion, noise, etc?). c12 2.2 u f c s 2.2 u f c ss 2.2 u f ct 10 u f l1 3 . 3 u h v ba t f u ll c a p a citive inverter vo u t in+ in- 1.2 v to 1.9 v -1.2 v to -1.9 v 0 v +vo u t -vo u t level detector dc/dc control hpvdd pv ss am06150
application information ts4621b 32/48 doc id 022194 rev 2 figure 76. efficiency comparison most audio signals have a crest factor higher than 6 db (10 db on average), which means that most of the time the music level is low. in this case, the setting of the internal dc/dc converters is low (1.2 v) and in this way, helps to minimize the power dissipation. when the audio signal amplitude increases due to a peak or louder music, the setting of the internal dc/dc converters increases to 1.9 v, automatically increasing the output dynamic range. this 1.9 v value remains until the end of the decay time. figure 77 shows a music sample played at high levels. figure 77. class-g operating with a music sample note: hpvdd/pvss voltages are crea ted internally by dc/dc converters. to avoid destruction of the ts4621b power amplifier, do not connect any external power supply on these pins. 0.1 1 10 0.1 1 10 100 t s 4601 cl ass ab t s 4621b cl ass g both ch a nnel s en ab led rl = 3 2 , f = 1khz vcc = 3 .6v, t a = 25 c cre s t f a ctor = 3 db efficiency (%) total output power (mw) hpvdd high 1.9v hpvdd low 1.2v pvss low -1.2v pvss high -1.9v music sample
ts4621b application information doc id 022194 rev 2 33/48 4.4 external component selection the ts4621b requires few external passive components to operate correctly. each component is described in the following sections. 4.4.1 step-down i nductor selection (l1) the ts4621b needs one inductor for the internal step-down dc/dc converter. this inductor must fit the following constraints: typical value: 2.2 h to 3.3 h (3.3 h is recommended). maximum current in operating mode: 400 ma minimum inductor value at maximum current: 1.5 h maximum inductor value at zero current: 4.3 h dc resistance: from 50 m up to 450 m ta bl e 1 4 shows the part number that should be used according to the inductor value. 4.4.2 step-down output capacitor selection (ct) for the internal dc/dc step-down converter, the ts4621b needs one output capacitor. the three criteria for selecting the output capacitor are the range value of the capacitor including self tolerance, dc variation and th e minimum esr value, which is mandatory to avoid oscillation of the converter. therefor e the following constraints must be observed. typical capacitor value: 10 f at dc = 0 v maximum capacitor value: 12 f at dc = 0 v minimum capacitor value: 4.8 f at dc = 2 v voltage range across this capacitor: from 1.1 v to 2 v minimum dc esr value: 5 m a ceramic capacitor in a 0603-type package is also recommended because of its close placement to the ts4621b, which makes it easier to minimize parasitic inductance and resistance that have a negative impact on the audio performance. table 14. recommended inductor manufacturer part number value murata lqm21pn3r3ngrd 3.3 h lqm2mpn3r3g0l 3.3 h lqm2mpn2r2g0l 2.2 h fdk mipsz2012d3r3 3.3 h mipsz2012d2r2 2.2 h
application information ts4621b 34/48 doc id 022194 rev 2 4.4.3 full capacitive inverter capacit ors selection (c12 and css) two capacitors (c12 and css) are needed for this internal dc/dc inverter. the three criteria for selecting theses capacitors are the range value of the capacitor including self tolerance, dc variation and the minimum esr to minimize power losses. typical capacitor value: 2.2 f +/-20 % voltage across these capacitors: from 1.1 v to 2 v minimum capacitor value: 1 f again, a ceramic capacitor in a 0603 or 0402-type package is also recommended because of their close placement to the ts4621b, wh ich makes it easier to minimize parasitic inductance and resistance that have a negative impact on the audio performance. 4.4.4 power supply decoupli ng capacitor selection (cs) a 2.2 f decoupling capacitor with low esr is recommended for positive power supply decoupling. packages such as the 0402 or 0603 are also recommended because of their close placement to the ts4621b, which makes it easier to minimize parasitic inductance. it is advised to choose a x5r dielectric for capa citor tolerance, and a 10 v dc rating voltage for 4.8 v operations (or a 6.3 v dc rating voltage for 3.6 v operations), to take into consideration the c/ v variation of this type of ceramic capacitor. an important parameter is the rated voltage of the capacitor. a 2.2 f/6.3 v capacitor used at 4.8 v dc typically loses about 40 % of its value. in fact, with a 4.8 v power supply voltage, the decoupling value is about 1.3 f instead of 2.2 f. because the decoupling capacitor influences the thd+n in the medium-to-high frequency region, this capacitor variation becomes decisive. in addition, less decoupling means higher overshoots, which can be problematic if they reach the power supply?s amr value (5.5 v). this is why, for a 2.2 f value, we recommend a 2.2 f/10 v, a 4.7 f/6.3 v or a ceramic capacitor with a low dc bias variation rated at 6.3 v. 4.4.5 input coupling c apacitor selection (cin) cin input coupling capacitors are mandatory for the ts4621b?s operation. they block any dc component coming from the audio signal source. cin with rin form a first-order high-pass filter and the -3 db cutoff frequency is: rin is the single-ended input impedance th at can be approximated at about rindiff/2. rin also depends on the gain setting. figure 19 provides the differential input impedance vs. gain. one can also see that rindiff is minimum for the maximum gain setting (that is, 4 db). table 15. recommended capacitor manufacturer part number value murata grm188r60j106me47 10 f, 6.3 v, x5r grm188r60j106me84 10 f, 6.3 v, x5r grm188r61e106me73 10 f, 25 v, x5r fc 3db ? () 1 2 rin cin -------------------------------------------- =
ts4621b application information doc id 022194 rev 2 35/48 therefore, in most cases, rin should be set to 4 db to calculate the minimum input capacitor cin. example: at maximum gain g = 4 db, rindiff/2 = k /2 = 17 k . however, to take into consideration the worst case, one has to use rindiff/2 = 25 k /2 = 12.5 k . in this case and for a -3 db cutoff frequency of 20 hz, cin = 0.64 f. the closest normalized value is 0.68 f but a 1 f capacitor is more suitable to take into consideration the capacitor tolerance +/-20 %. if the aim is to have the 20 hz at -1 db, the capacitor has to be multiplied by 1.96. as such, cin = 0.64 x 1.96 = 1.25 f. the closest normalized value would be 1.5 f or 2.2 f. 4.4.6 low-pass output filter (rout and cout) and iec 61000-4-2 esd protection the ts4621b is designed to operate with a passive first-order low-pass filter (as shown in figure 1. ). this low-pass filter is mandatory to ensure correct operation of the ts4621b over the volume range and output capacitance range vs. load. rout must have a value of 12 minimum and cout a value of 0.8 nf minimum up to 100 nf maximum. values of 12 and 1 nf are a good starting point for a design to be able to drive a classic headphone (16 , 32 , 60 ) and the line-in of any hi-fi system or sound card. the cutoff frequency of this filter (12 and 1 nf) is approximately 13 mhz and clearly above the audio band. however, this output rc filter is also a part of the iec 61000-4-2 esd protection. in most cases, this rc filter is designed with transient absorbers and the final solution can be a discrete solution or an integrated solution. st microelectronics? portfolio has many integrated solutions for esd, but one dedicated to headphone amplifiers in particular: ipad (a) reference emif02-av01f3. to fit the iec 61000-4-2 standard, this audio line ipad can be added to the output of the ts4621b as shown in figure 78 . a. copyright stmicroelectronics.
application information ts4621b 36/48 doc id 022194 rev 2 figure 78. typical application schematic with iec 61000-4-2 esd protection by adding this esd protection, the ts4621b complies with the iec 61000-4-2 level 4 standard on jack pins. our demonstration board has been tested using the same conditions as those outlined in the iec 61000-4-2 standard. results may differ depending on the layout of the pcb. 15 kv (air discharge) 8 kv (contact discharge) this ipad has an internal series resistor rout = 15 +/-20 % and an output capacitor cout = 3.2 nf +/-25 %. 4.4.7 integrated i nput low-pass filter the ts4621b has an integrated internal first-order low-pass filter with a -3 db cutoff frequency set at 65 khz and independent of the volume position. this integrated filter is present on each input and filters any out-of-band audio noise coming from the audio source. 4.5 single-ended input configuration the ts4621b can be used in a single-ended input configuration. inr- and inl- or inr+ and inl+ can be shorted to ground through input capacitors. all cin capacitors must have the same value to keep the same psrr performance as in a differential input configuration. figure 79 and figure 80 show how to connect the ts4621b. note the ground connection of each input. to avoid psrr issues resulting from any ground noise, this connection must be done on the ground of the audio source and not on the ground of the ts4621b itself. 1 2 3 j1 cin 1 f cin 1 f cin 1 f cin 1 f c12 2.2 f c s 2.2 f c ss 2.2 f ct 10 f l1 3 . 3 h v ba t i2c b us po s itive left inp u t po s itive right inp u t + - + - i2c neg a tive su pply po s itive su pply agnd c1 c2 s da s cl avdd inl- inl+ inr+ inr- vo u tl vo u tr cm s level detector level detector s w hpvdd pv ss neg a tive right inp u t neg a tive left inp u t a1 2 c 1 c a2 b2 gnd ip a d am06151
ts4621b application information doc id 022194 rev 2 37/48 figure 79. single-ende d input configuration1 figure 80. single-ended input configuration 2 ro u t 12 ohm s min. ro u t 12 ohm s min. co u t 0. 8 nf min. co u t 0. 8 nf min. cin 1 f cin 1 f cin 1 f cin 1 f 1 2 3 j1 c12 2.2 f c s 2.2 f c ss 2.2 f ct 10 f l1 3 . 3 h v ba t i2c bus + - + - i2c neg a tive su pply po s itive su pply agnd c1 c2 s da s cl avdd inl- inl+ inr+ inr- vo u tl vo u tr cm s level detector level detector s w hpvdd pv ss a u dio driver left o u tp u t right o u tp u t a u dio driver gro u nd am06152 ro u t 12 ohm s min. ro u t 12 ohm s min. co u t 0. 8 nf min. co u t 0. 8 nf min. cin 1 f cin 1 f cin 1 f cin 1 f 1 2 3 j1 c12 2.2 f c s 2.2 f c ss 2.2 f ct 10 f l1 3 . 3 h v ba t i2c bus + - + - i2c neg a tive su pply po s itive su pply agnd c1 c2 s da s cl avdd inl- inl+ inr+ inr- vo u tl vo u tr cm s level detector level detector s w hpvdd pv ss a u dio driver left o u tp u t right o u tp u t a u dio driver gro u nd am0615 3
application information ts4621b 38/48 doc id 022194 rev 2 the gain range in these configurations remains unchanged and is given by: with reference to figure 80. , note that the absolute phase in the audio band is 180. 4.5.1 layout recommendati ons for single-ended operation the connection location of each input that has to be set to ground is extremely important. incorrect connection location figure 81. incorrect ground connection for single-ended option if these inputs are connected to agnd (the ground of the ts4621b class-g), the output voltage can be expressed by the following simplified equation from an ac point of view. vout = av x (vaudio + vmc + vgndnoise) + vbatnoise x psrr (1) as shown in equation (1), any ground noise and any parasitic ac voltage on vmc is directly multiplied by the gain of the amplifier. if vmc can be totally controlled by the design of the audio source device (no parasitic ac voltage), it is not necessarily the case for vgndnoise. this noise can be significantly reduced by an adequate low impedance ground plane, but not totally eliminated. in practice, only ten m illivolts in the right fr equency rang e are enough to produce an audible parasitic sound in the headphone with a volume level as low as -20 db. voutlr vinlr gain = ro u t 12 ohm s min. ro u t 12 ohm s min. co u t 0. 8 nf min. co u t 0. 8 nf min. cin 1 f cin 1 f cin 1 f cin 1 f 1 2 3 j1 c12 2.2 f c s 2.2 f c ss 2.2 f ct 10 f l1 3 . 3 h v ba t i2c bus + - + - i2c neg a tive su pply po s itive su pply agnd c1 c2 s da s cl avdd inl- inl+ inr+ inr- vo u tl vo u tr cm s level detector level detector s w hpvdd pv ss a u dio driver left o u tp u t right o u tp u t vgndnoi s e v au diol v au dior vmc am06154
ts4621b application information doc id 022194 rev 2 39/48 correct connection location as shown in figure 82 , the best option is to route the single-ended signal in parallel with the ac ground line of the other input. the ac grounded terminal must be routed in parallel to the audio signal and grounded with the ground of the audio source. figure 82. correct ground connection for single-ended option in this configuration, the ac output voltage is: vout = av x (vaudio + vmc) + vgndnoise x cmrr + vbatnoise x psrr (2) in equation (2), the ground noise is attenuated by the performance of the cmrr. in practice, 50 db of cmrr and ten millivolts for ground no ise gives an output of approximately 30 v, which is normally too low to be perceptible in the headphone. if vmc is also totally controlled by the design of the audio source, equation (2) becomes: vout = av x vaudio + vbatnoise x psrr (3) like in differential mode, the main contributor for audio signal degradation is the ac noise voltage on vbat. thanks to the ts4621b?s very high psrr that can attenuate gsm burst noise, equation (3) becomes: vout = av x vaudio (4) ro u t 12 ohm s min. ro u t 12 ohm s min. co u t 0. 8 nf min. co u t 0. 8 nf min. cin 1 f cin 1 f cin 1 f cin 1 f 1 2 3 j1 c12 2.2 f c s 2.2 f c ss 2.2 f ct 10 f l1 3 . 3 h v ba t i2c bus + - + - i2c neg a tive su pply po s itive su pply agnd c1 c2 s da s cl avdd inl- inl+ inr+ inr- vo u tl vo u tr cm s level detector level detector s w hpvdd pv ss a u dio driver left o u tp u t right o u tp u t vgndnoi s e v au diol v au dior vmc am06155
application information ts4621b 40/48 doc id 022194 rev 2 4.6 startup phase the ts4621b uses different techniques to reduce the dc current consumption and offer a pop-and-click performance close to none. 4.6.1 auto zero technology during the start-up phase, the differential output voltage is sensed and adjusted to 0 v (+/-500 v) to avoid any pop noise when the amplifier becomes operational. this also helps to minimize extra current consumption due to the load (icc-extra = voutdc / rload). 4.6.2 input impedance the ts4621b requires input coupling capacitors. the usual lowest frequency used for the headphone is close to 20 hz. this frequency means a constant time for a first-order high- pass filter of approximately 1 / (2 x pi x 20) = 8 ms. to achieve 95 % of the capacitor?s charge, it is necessary to wait 3 x 8 ms = 24 ms, which is out of range for a device with a fast start-up time. because of the mismatching of all input capacitors and input resistors, if it is decided to start the ts4621b at a time of 8 ms, a voltage difference at the inputs (multiplied by the gain) can create a voltage step on the output and consequently a pop noise. to avoid this issue during the starting phase, the ts4621b accelerates the charging of the input capacitors by reducing the input impedance to 2 k . in such a case, for a 1 f capacitor the 95 % charge is reached in 6 ms. as the start-up time of ts4621b is 12 ms, there remains sufficient ti me to fully charge the input capacitors and as such eliminate any pop noise. 4.7 layout recommendations particular attention must be given to the correct layout of the pcb traces and wires between the amplifier, load and power supply (in most cases, the battery of the cellular phone). the power and ground traces are critical si nce they must provide adequate energy and grounding for all circuits. good practice is to use short and wide pcb traces to minimize voltage drops and parasitic inductance. a track with a width of at least 200 m for a copper thickness of 18 m is recommended for bringing energy to the amplifier from the battery. proper grounding guidelines help improve audio performances, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. it is also recommended to use a large-area and multi-via ground plane to minimize parasitic impedance. a multi-layer pcb board allows double or multiple ground planes to be implemented. most of the time, the top and bottom layers are used as ground planes and provide shielding for tracks routed on the intermediate layers. in addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used. the copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize the trace resistances.
ts4621b application information doc id 022194 rev 2 41/48 4.7.1 common mode sense layout the ts4621b implements a common-mode sense pin to correct any voltage differences that might occur between the return of the headphone jack and the agnd of the device that can create parasitic noise in the headphone and/or line out. the solution to strongly reduce and practically eliminate this noise consists in connecting the headphone jack ground to the cms pin. this pin senses the difference of potential (voltage noise) between the ts4621b ground and the headphone ground. thanks to the frequency response and the attenuation of the common-mode sense pin, this noise is removed from the ts4621b outputs. figure 83. common mode sense layout example common mode sense pin output jack connector ground plane
application information ts4621b 42/48 doc id 022194 rev 2 4.8 demonstration board a demonstration board is available at www.st.com with the order code steval-cca025v1. the following figures show the demonstration board schematics and associated pcb layouts. figure 84. demonstration board schematic 3 4 14 1 3 u2b kp1040 5 6 12 11 u2c kp1040 1 2 16 15 u2a kp1040 1 6 2 7 3 8 4 9 5 j2 db9 gnd2 gnd2 vcc gnd gnd gnd gnd2 gnd rt s d s r txd dtr r 3 1k r9 1k r6 10k r7 10k r 8 2k2 d1 1n414 8 d2 1n414 8 r5 100 gnd r2 12 r1 12 c9 2.2 nf c10 2.2 nf gnd gnd cn5 c4 2.2 f c5 2.2 f c7 2.2 f c6 2.2 f gnd gnd vcci2c gnd cn4 1 2 3 j1 gnd vcci2c cn2 left inp u t cn9 right inp u t cn6 s cl cn7 s da cn1 power cn 3 left o u tp u t right o u tp u t s da s cl s cl s da r4 1 8 0 r s -2 3 2 to i2c converter t s 4621b m a in a pplic a tion c 3 2.2 f c1 2.2 f c2 2.2 f c 8 10 f l1 3 . 3 u h gnd gnd gnd gnd hpvdd vcc gnd gnd q1 gnd q2 gnd q 3 cn 8 vcci2c + - + - i2c neg a tive su pply po s itive su pply agnd c1 c2 s da s cl avdd inl- inl+ inr+ inr- vo u tl vo u tr cm s a4 b4 b1 a 3 b 3 c2 b2 c1 d4 c4 c 3 a2 a1 d1 d2 d 3 level detector level detector s w hpvdd pv ss u1 t s 4621b am06156
ts4621b application information doc id 022194 rev 2 43/48 figure 85. copper layers figure 86. copper layer and overlay layers top layer mid layer 1 mid layer 2 bottom layer top overlay bottom overlay
package information ts4621b 44/48 doc id 022194 rev 2 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 87. ts4621b footprint recommendation figure 88. pinout 150 m min. 400 m 400 m 400 m 400 m pcb p a d s ize: = 260 m m a xim u m = 220 m recommended 75 m min. 100 m m a x. tr a c k not s oldered m as k opening s older m as k opening: = 3 00 m min (for 260 m di a meter p a d) p a d in c u 1 8 m with fl as h nia u (2-6 m, 0.2 m m a x.) top view ( ba ll s a re u nderne a th) bottom view avdd s w inl - c1 cm s s da agnd c2 hpvdd voutl voutr inl+ inr+ pv ss s cl inr - 4 3 21 a b c d c1 c2 hpvdd avdd agnd pv ss cm s voutr voutl inl+ inr+ inl - inr - s cl s da s w 12 3 4 a b c d
ts4621b package information doc id 022194 rev 2 45/48 figure 89. marking (top view) figure 90. flip-chip - 16 bumps figure 91. device orientation in tape pocket logo: st symbol for lead-free: e part number: 21 x digit: assembly code date code: yww the dot marks pin a1 21x yww e 21x yww e 400 m 400 m 1650 m 600 m 1650 m die size: 1.65 mm x 1.65 mm 30 m die height (including bumps): 600 m 55 m bump diameter: 250 m 40 m bump height: 205 m 35 m die height: 395 m 20 m pitch: 400 m 40 m coplanarity: 50 m max 4 1.5 u s er direction of feed 8 die s ize x + 70 m die s ize y + 70 m 4 all dimen s ion s a re in mm a 1 a 1
ordering information ts4621b 46/48 doc id 022194 rev 2 6 ordering information table 16. order codes order code temperature range package packing marking TS4621BEIJT -40c to +85c flip-chip tape & reel 21
ts4621b revision history doc id 022194 rev 2 47/48 7 revision history table 17. document revision history date revision changes 06-sep-2011 1 initial release. 12-sep-2011 2 updated table 10: summary of control registers on page 25 updated section 4.1.2: control register cr1 - address 1 on page 27
ts4621b 48/48 doc id 022194 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of TS4621BEIJT

	To Download TS4621BEIJT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .